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IP4776CZ38
Fully integrated HDMI interface with level shifter, ESD and backdrive protection
Rev. 04 -- 12 June 2007 Product data sheet
1. General description
The IP4776CZ38 is designed for HDMI host-interface protection. The IP4776CZ38 includes level shifting for the DDC channels and backdrive protection for HDMI as well as high-level ESD protection diodes for the TMDS signal lines. The level shifting function is required when the receiver operates at a supply voltage lower than the external devices to protect the I/Os against over voltages. The IP4776CZ38 contains four N-channel MOSFETs to provide this level shifting function. Furthermore, all TMDS intra-pairs are protected by a special diode configuration offering an ultra low line capacitance of 0.7 pF only. These diodes provide protection to downstream components from ESD voltages up to 8 kV contact according to the IEC 61000-4-2, level 4 standard.
2. Features
I Pb-free and RoHS compliant, Dark Green I Integrated high-level ESD protection, level shifting and backdrive protection I All TMDS lines with integrated rail-to-rail clamping diodes with downstream ESD protection of 8 kV according to IEC 61000-4-2, level 4 standard I Matched 0.5 mm trace spacing I Bidirectional level shifting N-channel FETs provided for DDC clock and data channels I TMDS lines with 0.05 pF matching of capacitance between the TMDS pairs I Ultra low line capacitance of 0.7 pF per channel I HDMI 1.3 compliant I Backdrive protection I 38-pin TSSOP lead-free package
3. Applications
I The IP4776CZ38 is designed for HDMI receiver and transmitter port protection, level shifting and backdrive protection e.g.: N TV N Graphics card N Set-top box N DVD N Digital media adapter N Game console
NXP Semiconductors
IP4776CZ38
Fully integrated HDMI interface with level shifter
4. Ordering information
Table 1. Ordering information Package Name IP4776CZ38 TSSOP38 Description plastic thin shrink small outline package; 38 leads; body width 4.4 mm; lead pitch 0.5 mm Version SOT510-1 Type number
5. Functional diagram
TMDS_D2+ TMDS_D1+ TMDS_BIAS TMDS_D0+ TMDS_CLK+ VCC(5V0)
TMDS_D2-
TMDS_D1-
TMDS_GND
TMDS_D0-
TMDS_CLK-
VCC(3V3) TMDS_BIAS
VCC(3V3) TMDS_BIAS
DDC_CLK_IN
DDC_CLK_OUT
CEC_IN
CEC_OUT
VCC(3V3) TMDS_BIAS
VCC(3V3) TMDS_BIAS
HOT_PLUG_DET_IN
HOT_PLUG_DET_OUT
DDC_DAT_IN
DDC_DAT_OUT
001aae863
Fig 1. Functional diagram
IP4776CZ38_4
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 -- 12 June 2007
2 of 13
NXP Semiconductors
IP4776CZ38
Fully integrated HDMI interface with level shifter
6. Pinning information
6.1 Pinning
VCC(5V0) VCC(3V3) GND TMDS_D2+ TMDS_GND n.c. TMDS_D1+ TMDS_GND n.c.
1 2 3 4 5 6 7 8 9
38 n.c. 37 TMDS_BIAS 36 GND 35 n.c. 34 TMDS_GND 33 TMDS_D2- 32 n.c. 31 TMDS_GND 30 TMDS_D1-
TMDS_D0+ 10 TMDS_GND 11 n.c. 12 TMDS_CLK+ 13 TMDS_GND 14 n.c. 15 CEC_IN 16 DDC_CLK_IN 17 DDC_DAT_IN 18 HOT_PLUG_DET_IN 19
IP4776CZ38
29 n.c. 28 TMDS_GND 27 TMDS_D0- 26 n.c. 25 TMDS_GND 24 TMDS_CLK- 23 CEC_OUT 22 DDC_CLK_OUT 21 DDC_DAT_OUT 20 HOT_PLUG_DET_OUT
001aae862
Fig 2. Pin configuration
6.2 Pin description
Table 2. Symbol VCC(5V0) VCC(3V3) GND TMDS_D2+ TMDS_GND n.c. TMDS_D1+ TMDS_GND n.c. TMDS_D0+ TMDS_GND n.c. TMDS_CLK+ TMDS_GND n.c. Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Description supply voltage bias supply voltage for the level shifters ground reference[1] D2+ TMDS ESD protection[2] ground reference[1] not connected[2] D1+ TMDS ESD protection[2] ground reference[1] not connected[2] D0+ TMDS ESD protection[2] ground reference[1] not connected[2] CLK+ TMDS ESD protection[2] ground reference[1] not connected[2]
IP4776CZ38_4
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 -- 12 June 2007
3 of 13
NXP Semiconductors
IP4776CZ38
Fully integrated HDMI interface with level shifter
Pin description ...continued Pin 16 17 18 19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Description CEC input[3] DDC clock input[3] DDC data input[3] hot plug detection input[3] hot plug detection output[4] DDC data output[4] DDC clock output[4] CEC output[4] CLK- TMDS ESD protection[2] ground reference[1] not connected[2] D0- TMDS ESD protection[2] ground reference[1] not connected[2] D1- TMDS ESD protection[2] ground reference[1] not connected[2] D2- TMDS ESD protection[2] ground reference[1] not connected[2] ground reference[1] bias for TMDS ESD protection and bias for level shifter output ESD protection. This pin must be connected to a 0.1 F capacitor. not connected
Table 2. Symbol CEC_IN
DDC_CLK_IN DDC_DAT_IN HOT_PLUG_DET_IN DDC_DAT_OUT DDC_CLK_OUT CEC_OUT TMDS_CLK- TMDS_GND n.c. TMDS_D0- TMDS_GND n.c. TMDS_D1- TMDS_GND n.c. TMDS_D2- TMDS_GND n.c. GND TMDS_BIAS
HOT_PLUG_DET_OUT 20
n.c.
[1] [2] [3] [4]
38
Pins GND and TMDS_GND are internally connected. This pin always has to be connected to the pin on the opposite location of the IC via a PCB track to guarantee correct functionality; see Figure 3, Figure 4 and Figure 5. VCC(3V3) referenced logic level in. VCC(5V0) referenced logic level out.
IP4776CZ38_4
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 -- 12 June 2007
4 of 13
NXP Semiconductors
IP4776CZ38
Fully integrated HDMI interface with level shifter
7. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI VESD Parameter supply voltage input voltage electrostatic discharge voltage at input pins signal pins; IEC 61000-4-2, level 4 contact air discharge all other pins; MIL-STD-883 Method 3015 (human body model) contact air discharge Tstg
[1]
[1] [2] [2]
Conditions
Min GND - 0.5 GND - 0.5 -8 -15
Max 5.5 5.5 +8 +15
Unit V V kV kV
-2 -2 -55
+2 +2 +125
kV kV C
storage temperature
Signal pins: TMDS_D2+, TMDS_D2-, TMDS_D1+, TMDS_D1-, TMDS_D0+, TMDS_D0-, TMDS_CLK+, TMDS_CLK-, CEC_OUT, DDC_DAT_OUT, DDC_CLK_OUT, HOT_PLUG_DET_OUT. This measurement is performed with a 0.1 F external capacitor on pin TMDS_BIAS.
[2]
8. Recommended operating conditions
Table 4. Symbol Tamb Recommended operating conditions Parameter ambient temperature Conditions Min -40 Typ Max +85 Unit C
9. Characteristics
Table 5. Characteristics Tamb = 25 C; unless otherwise specified. Symbol ICC(5V0) ICC(3V3) Ibck(out-VCC5V0) Parameter supply current (5.0 V) supply current (3.3 V) back current from output / TMDS pins to VCC(5V0) Zener diode breakdown voltage reverse leakage current forward voltage TMDS channel capacitance VCC(5V0) = 5 V; f = 1 MHz; Vbias = 2.5 V
[2]
Conditions VCC(5V0) = 5.0 V VCC(3V3) = 3.3 V signal pins; powered down; VCC(5V0) < VO(ch)
[1]
Min -
Typ 1 0.1
Max 130 5 0.5
Unit A A A
VBRzd IL(r) VF Cch(TMDS)
I = 1 mA per TMDS channel; VI = 3.0 V
6 -
0.7 0.7
9 1 -
V A V pF
IP4776CZ38_4
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 -- 12 June 2007
5 of 13
NXP Semiconductors
IP4776CZ38
Fully integrated HDMI interface with level shifter
Table 5. Characteristics ...continued Tamb = 25 C; unless otherwise specified. Symbol Cch(TMDS) Cch(mutual) Parameter TMDS channel capacitance difference mutual channel capacitance Conditions VCC(5V0) = 5 V; f = 1 MHz; Vbias = 2.5 V between signal pin and pin n.c.; VCC(5V0) = 0 V; f = 1 MHz; Vbias = 2.5 V VCC(5V0) = 0 V; f = 1 MHz; Vbias = 2.5 V
[2]
Min -
Typ 0.05 0.07 4
Max 6
Unit pF pF pF
[2]
CI(ch-GND)(levsh) level shifting input capacitance from channel to ground Rdyn dynamic resistance
[2]
I = 1 A; IEC 61000-4-5/9 positive transient negative transient [3]
2.4 1.3 8
-
V
VCL(ch)trt(pos)
positive transient channel clamping voltage on-state voltage drop
VESD = 8 kV
-
Von
[1]
VCC(3V3) = 2.5 V; VS = GND; IDS = 3 mA
[4]
-
85
140
mV
Signal pins: TMDS_D2+, TMDS_D2-, TMDS_D1+, TMDS_D1-, TMDS_D0+, TMDS_D0-, TMDS_CLK+, TMDS_CLK-, CEC_OUT, DDC_DAT_OUT, DDC_CLK_OUT, HOT_PLUG_DET_OUT. This parameter is guaranteed by design. This measurement is performed with a 0.1 F external capacitor on pin TMDS_BIAS. For level shifting N-FET.
[2] [3] [4]
IP4776CZ38_4
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 -- 12 June 2007
6 of 13
NXP Semiconductors
IP4776CZ38
Fully integrated HDMI interface with level shifter
10. Application information
IP4776CZ38
VCC(5V0) VCC(3V3) GND 1 2 3 38 37 36 n.c. TMDS_BIAS GND TMDS_D2+ TMDS_GND TMDS_D2- TMDS_D1+ TMDS_GND TMDS_D1- TMDS_D0+ TMDS_GND TMDS_D0- TMDS_CLK+ TMDS_GND TMDS_CLK- CEC HDMI CONNECTOR
C_BYP 100 nF
TMDS_D2+ 4 TMDS_GND 5 6 n.c. TMDS_D1+ 7 TMDS_GND
35 n.c. 34 TMDS_GND
33 TMDS_D2- 32 n.c. TMDS_GND
8 9
31
30 TMDS_D1- 29 n.c. 28 TMDS_GND
n.c. TMDS_D0+ 10 TMDS_GND 11 12 n.c. TMDS_CLK+ 13 TMDS_GND 14 15 n.c. CEC_IN 16 23 CEC_OUT 26 n.c. TMDS_GND 25 24 TMDS_CLK-
HDMI TRANSMITTER
27 TMDS_D0-
n.c. DDC_CLK_IN DDC_DAT_IN HOT_PLUG _DET_IN 17 18 19 22 21 20 DDC_CLK_OUT DDC_DAT_OUT HOT_PLUG_ DET_OUT DDC_CLK DDC_DAT GND +5 V HOT_ PLUG_DET
R_PD 15 k
R_CEC 100 k R_Clock 47 k
R_Data 47 k
R_CEC 27 k R_Clock 1.5 k
R_Data 1.5 k
VCC(3V3)
VCC(3V3) VCC(5V0)
001aae865
Use tapered tracks to connect adjacent TMDS+ and TMDS- pins with the opposite n.c. pins; see Figure 5. Use tapered tracks to connect adjacent TMDS+ and TMDS- pins with the HDMI connector; see Figure 5. Use tapered tracks to connect adjacent TMDS+ and TMDS- pins with the HDMI transmitter; see Figure 5.
Fig 3. HDMI transmitter application layout diagram
IP4776CZ38_4
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 -- 12 June 2007
7 of 13
NXP Semiconductors
IP4776CZ38
Fully integrated HDMI interface with level shifter
IP4776CZ38
VCC(5V0) VCC(3V3) GND 1 2 3 38 37 36 n.c. TMDS_BIAS
C_BYP 100 nF
GND TMDS_D2+ TMDS_GND TMDS_D2- TMDS_D1+ TMDS_GND TMDS_D1- TMDS_D0+ TMDS_GND TMDS_D0- TMDS_CLK+ TMDS_GND TMDS_CLK- CEC HDMI CONNECTOR
TMDS_D2+ 4 TMDS_GND
35 n.c. TMDS_GND
5 6
34
33 TMDS_D2- 32 n.c. 31 TMDS_GND
n.c. TMDS_D1+ 7 TMDS_GND
8 9
30 TMDS_D1- 29 n.c. TMDS_GND 28 27 TMDS_D0- 26 n.c. TMDS_GND 25 24 TMDS_CLK- CEC_OUT
n.c. TMDS_D0+ 10 TMDS_GND HDMI RECEIVER 11 12 n.c. TMDS_CLK+ 13 TMDS_GND 14 15 n.c. CEC_IN 16 23
n.c. DDC_CLK_IN DDC_DAT_IN HOT_PLUG _DET_IN 17 18 22 21 20 DDC_CLK_OUT DDC_DAT_OUT HOT_PLUG _DET_OUT
R_Clock 47 k R_CEC 100 k R_Clock 47 k R_Data 47 k
DDC_CLK DDC_DAT GND +5 V
R_Data 47 k R_HP 1.0 k
1 2 3 4 EEPROM
8 7 6 5
R_CEC 27 k R 10 k
HOT_PLUG _DET
C_HP 100 nF
VCC(3V3)
R_DDC 100
VCC(3V3) VCC(5V0)
001aae961
Use tapered tracks to connect adjacent TMDS+ and TMDS- pins with the opposite n.c. pins; see Figure 5. Use tapered tracks to connect adjacent TMDS+ and TMDS- pins with the HDMI connector; see Figure 5. Use tapered tracks to connect adjacent TMDS+ and TMDS- pins with the HDMI receiver; see Figure 5.
Fig 4. HDMI receiver application layout diagram
IP4776CZ38_4
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 -- 12 June 2007
8 of 13
NXP Semiconductors
IP4776CZ38
Fully integrated HDMI interface with level shifter
D2- D1+ D1-
D2+
3 5V 3V CC C VC GND V
Integrated Discretes
TMDS_VDD
IDs_boar d20_rev4 IDs 11/05
8 CB Z3 P Cn 76 tio 47 ica IP p l Ap ug pl ta ot a H C_dlk Dc D C_ D in D C_ E C
D0+ D0-
CLK+
CLK-
IP4776CZ38
001aae864
Fig 5. Layout proposal of printed-circuit board
IP4776CZ38_4
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 -- 12 June 2007
9 of 13
NXP Semiconductors
IP4776CZ38
Fully integrated HDMI interface with level shifter
11. Package outline
TSSOP38: plastic thin shrink small outline package; 38 leads; body width 4.4 mm; lead pitch 0.5 mm
SOT510-1
D
E
A X
c y HE vMA
Z
38
20
A2 pin 1 index A1
(A 3)
A
Lp L
1
e bp
19
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.85 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 9.8 9.6 E (2) 4.5 4.3 e 0.5 HE 6.4 L 1 Lp 0.7 0.5 v 0.2 w 0.08 y 0.08 Z (1) 0.49 0.21
8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT510-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION
ISSUE DATE 03-02-18 05-11-02
Fig 6. Package outline SOT510-1 (TSSOP38)
IP4776CZ38_4 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 -- 12 June 2007
10 of 13
NXP Semiconductors
IP4776CZ38
Fully integrated HDMI interface with level shifter
12. Abbreviations
Table 6. Acronym CEC DDC DVD ESD FET HDM HDMI MOSFET RoHS TMDS Abbreviations Description Consumer Electronics Control Data Display Channel Digital Video Disk ElectroStatic Discharge Field Effect Transistor High-Definition Multimedia High-Definition Multimedia Interface Metal Oxide Semiconductor Field Effect Transistor Restriction of the use of certain Hazardous Substances Transition Minimized Differential Signaling
13. Revision history
Table 7. Revision history Release date 20070612 Data sheet status Product data sheet Change notice Supersedes IP4776CZ38_3 Document ID IP4776CZ38_4 Modifications: IP4776CZ38_3 Modifications:
* * * * * *
Section 2; update of first feature. Table 5; update of Max. value of back current from output / TMDS pins to VCC(5V0). Product data sheet IP4776CZ38_2 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 5; update of supply current (5.0 V), Min and Typ values Update of Figure 3 and Figure 4 Product data sheet Product data sheet IP4776CZ38_1 -
20070125
IP4776CZ38_2 IP4776CZ38_1
20060918 20060714
IP4776CZ38_4
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 -- 12 June 2007
11 of 13
NXP Semiconductors
IP4776CZ38
Fully integrated HDMI interface with level shifter
14. Legal information
14.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
14.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
15. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
IP4776CZ38_4
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 -- 12 June 2007
12 of 13
NXP Semiconductors
IP4776CZ38
Fully integrated HDMI interface with level shifter
16. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Application information. . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information. . . . . . . . . . . . . . . . . . . . . 12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 June 2007 Document identifier: IP4776CZ38_4

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